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The effects of edge irregularity and mixed edge shapes on the characteristics of graphene nanoribbon transistors are examined by self-consistent atomistic simulations based on the non-equilibrium Green's function formalism. The minimal leakage current increases due to the localized states induced in the band gap, and the on-current decreases due to smaller quantum transmission and the self-consistent electrostatic effect in general. Although the ratio between the on-current and minimal leakage current decreases, the transistor still switches even in the presence of edge roughness. The variation between devices, however, can be large, especially for a short channel length.
It is usually assumed that tunneling current is fairly independent of temperature. By performing an atomistic transport simulation, we show, to the contrary, that the subthreshold tunneling current in a graphene nanoribbon (GNR) band-to-band tunneling transistor (TFET) should show significant and non-linear temperature dependence. Furthermore, the nature of this non-linearity changes as a function of source/drain doping and vertical electric field, indicating that such non-linearity, if properly understood, may provide important insights into the tunneling phenomena. Finally, by developing a pseudo-analytical method, we predict that such temperature dependence is not unique to GNR but should rather be a general behavior for any band-to-band tunneling transistor independent of the channel material.
Comment: *These authors contributed equally to this work. 33 pages, 12 figures. The replacement of this manuscript is because a typo found in program which changes the quantitative results by factor of 2. The qualitative features and conclusions are not changed
Using self-consistent quantum transport simulation on realistic devices, we show that InAs band-to-band Tunneling Field Effect Transistors (TFET) with a heavily doped pocket in the gate-source overlap region can offer larger ON current and steeper subthreshold swing as compared to conventional tunneling transistors. This is due to an additional tunneling contribution to current stemming from band overlap along the body thickness. However, a critical thickness is necessary to obtain this advantage derived from 'vertical' tunneling. In addition, in ultra small InAs TFET devices, the subthreshold swing could be severely affected by direct source-to-drain tunneling through the body.
Mode space approach has been used so far in NEGF to treat phonon scattering for computational efficiency. Here we perform a more rigorous quantum transport simulation in real space to consider interband scatterings as well. We show a seamless transition from ballistic to dissipative transport in graphene nanoribbon transistors by varying channel length. We find acoustic phonon (AP) scattering to be the dominant scattering mechanism within the relevant range of voltage bias. Optical phonon scattering is significant only when a large gate voltage is applied. In a longer channel device, the contribution of AP scattering to the dc current becomes more significant.
Using 2-D self-consistent ballistic quantum transport simulations, we investigate the short-channel behavior of graphene field-effect transistors and its impact on the device transconductance and subsequently the intrinsic cut-off frequency (fT). Although with thin oxides, fT expectedly scales inversely with the gate length, significant band-to-band tunneling at OFF state leads to a departure from this trend in case of thick oxides. We also examine the effect of achieving better electrostatics at the cost of increased gate capacitance and illustrate that this can indeed degrade the fT. These considerations should be implicit in the optimization of graphene transistors for high-frequency applications.
A vertical partial gate carbon nanotube (CNT) field-effect transistor (FET), which is amenable to the vertical CNT growth process and offers the potential for a parallel CNT array channel, is simulated using a self-consistent atomistic approach. We show that the underlap between the gate and the bottom electrode (required for isolation between electrodes) is advantageous for transistor operation because it suppresses ambipolar conduction. A vertical CNTFET with a gate length that covers only 1/6 of the channel length has a much smaller minimum leakage current than one without underlap, while maintaining comparable on current. Both n-type and p-type transistor operations with balanced performance metrics can be achieved on a single partial gate FET by using proper bias schemes. Even with a gate underlap, it is demonstrated that increa...
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