Type

Database

Creator

Date

Thumbnail

Search results

1,412 records were found.

This chapter provides a unified introductory account of the estimation of the parameters of continuous-time systems using data compression based on a number of previous publications
Targeting at the emerging issues in recent years, manufacturing research has been focusing on improving flexibility, dynamism, agility and productivity for manufacturing in the 21st century, particularly in distributed and collaborative environments. Various Web-based and AI-based tools have been developed to deal with issues in process simulation, production planning, resource scheduling, and supply chain management. Many research projects have been devoted to improving product quality and manufacturing process efficiency targeting manufacturing uncertainty. This special issue titled "Distributed and Collaborative Manufacturing for the 21st Century" brings to the readers some of the state-of-the-art and new achievements in modern manufacturing research. There are nine papers in this special and their synopses are provided below.
[[abstract]]The charge-to-breakdown (Qbd) for p+-poly-Si MOS capacitors under positive and negative gate-bias stress was investigated. Among the various boron-implanted poly-Si samples, Qbd(+) increases with dopant concentration, but Qbd(-) decreases with the boron concentration. Meanw ile a large difference was found between the Qbd(+) and Qbd(-) values. Evidence for various degree of band bending of poly-Si was observed from C-V and Fowler-Nordheim tunneling measurements. From gate-voltage shift (ΔVg) data after constant current stress, the centroid of the generated positive trapped charge can be determined. We modified the charge-trapping model to explain the above Qbd behavior. Hole trapping is the cause of oxide breakdown. The observed difference between gate-positive and gate-negative Qbd is due to a polarity-dependent critical t...
[[abstract]]In current industrial practice, critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. The assumption of discrete timing models can be invalidated by delay effects in the deep submicron domain, where timing defects and process variation are statistical in nature. In this paper, we study the problem of optimizing critical path selection, under both fixed delay and statistical delay assumptions. With a novel problem formulation and new theoretical results, we prove that the problem in both cases are computationally intractable. We then discuss practical heuristics and their theoretical performance bounds, and demonstrate that among all heuristics under consideration, only one i...
[[abstract]]In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.
[[abstract]]In this paper, an effective algorithm is presented for multilevel circuit clustering for delay minimization, and is applicable to hierarchical field programmable gate arrays. With a novel graph contraction technique, which allows some crucial delay information of a lower-level clustering to be maintained in the contracted graph, our algorithm recursively divides the lower-level clustering into the next higher-level one in a way that each recursive clustering step is accomplished by applying a modified single-level circuit clustering algorithm based on . We test our algorithm on the two-level clustering problem and compare it with the latest algorithm in . Experimental results show that our algorithm achieves, on average, 12% more delay reduction when compared to the best results (from TLC with full node-duplication) in . In...
[[abstract]]Critical path selection is an indispensable step for testing of small-size delay defects. Historically, this step relies on the construction of a set of worst-case paths, where the timing lengths of the paths are calculated based upon discrete-valued timing models. The assumption of discrete-valued timing models may become invalid for modeling delay effects in the deep submicron domain, where the effects of timing defects and process variations are often statistical in nature. This paper studies the problem of critical path selection for testing small-size delay defects, assuming that circuit delays are statistical. We provide theoretical analysis to demonstrate that the new path-selection problem consists of two computationally intractable subproblems. Then, we discuss practical heuristics and their performance with respec...
[[abstract]]Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths, based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvement...
[[abstract]]We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.
[[abstract]]A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there could be a large difference in the number of structurally and functionally testable delay faults. However, this difference is usually calculated based only on logic constraints. It is unclear how this difference would change if timing constraints were taken into consideration, especially when using statistical timing models. In this paper, our goal is to better understand how structural and functional test strategies might affect the delay test quality and consequently, change our perception of the delay test results.
Want to know more?If you want to know more about this cutting edge product, or schedule a demonstration on your own organisation, please feel free to contact us or read the available documentation at http://www.keep.pt/produtos/retrievo/?lang=en