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[[abstract]]The linear discriminant function classifier is a widely used but computationally demanding method in statistical pattern recognition. This paper describes a bit-level systolic array for the linear discriminant function classifier to improve its processing speed. The system includes a new scheme for inner product computation, which not only has 100% efficiency but also gains a speed improvement over a previous method, and yields classification results at an average rate of one per B cycles of the array, where B is the wordlength of the input data. The throughout is higher than those of the related bit level arrays described previously.
[[abstract]]Bit-level systolic architectures based on an inner-product computation scheme for finite-impulse response (FIR) and infinite-impulse-response (IIR) digital are presented. The FIR filter structure is optimized in the sense that for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required
[[abstract]]The design and implementation of a linear brushless DC motor (LBDCM) drive with robust position control are presented. Hall-effect sensors and linear encoders are employed to obtain information of moving member position. A simple but practical zeroing approach is proposed to correct the phase errors of current commands due to the mechanical installation misalignment of Hall-effect sensors. Then a current-controlled PWM inverter is properly designed to yield excellent armature current tracking control characteristics. As to position control, the dynamic model of the LBDCM drive is first estimated from measurements. Then a two-degrees-of-freedom controller is quantitatively designed to meet the given position-control specifications. A robust controller is designed to reduce the control performance degradation due to system pa...
Clustering is one of the most important tasks for geographic knowledge discovery. However, existing clustering methods have two severe drawbacks for this purpose. First, spatial clustering methods have so far been mainly focused on searching for patterns within the spatial dimensions (usually 2D or 3D space), while general-purpose high-dimensional (multivariate) clustering methods have very limited power in recognizing spatial patterns that involve neighbors. Secondly, existing clustering methods tend to be ‘closed’ and are not geared toward allowing the interaction needed to effectively support a human-led exploratory analysis. The contribution of the research includes three parts. (1) Develop an effective and efficient hierarchical spatial clustering method, which can generate a 1-D spatial cluster ordering that preserves all the hie...
The diversity of hardware components within a single system calls for strategies for efficient cross-device data processing. For example, existing approaches to CPU/GPU co-processing distribute individual relational operators to the "most appropriate" device. While pleasantly simple, this strategy has a number of problems: it may leave the "inappropriate" devices idle while overloading the "appropriate" device and putting a high pressure on the PCI bus. To address these issues we distribute data among the devices by partially decomposing relations at the granularity of individual bits. Each of the resulting bit-partitions is stored and processed on one of the available devices. Using this strategy, we implemented a processor for spatial range queries that makes efficient use of all available devices. The performance gains achieved indi...
We consider the problem of finding an optimal design under a Poisson regression model with a log link, any number of independent variables, and an additive linear predictor. Local D-optimality of a class of designs is established through use of a canonical form of the problem and a general equivalence theorem. The results are applied in conjunction with clustering techniques to obtain a fast method of finding designs that are robust to wide ranges of model parameter values. The methods are illustrated through examples.
[[abstract]]To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variablelength encodings for instructions, and special data paths are frequently adopted. This creates challenges to deploy software toolkits for new embedded DSP processors. This article presents our methods and experiences to develop software and toolkit flows for PAC (Parallel Architecture Core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger, and DSP micro-kernels. We first retarget Open Research Compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, th...
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