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This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory dev...
Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory circuit, this paper investigates process repeatability, device uniformity in single-dot memory arrays, device scalability, and process transferability to an industrial application.
The Braess paradox, known for traffic and other classical networks, lies in the fact that adding a new route to a congested network in an attempt to relieve congestion can counter-intuitively degrade the overall network performance. Recently, we have extended the concept of Braess paradox to semiconductor mesoscopic networks, whose transport properties are governed by quantum physics. In this paper, we demonstrate theoretically that, alike in classical systems, congestion plays a key role in the occurrence of a Braess paradox in mesoscopic networks.
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